The present invention relates to methods of controlling the operation of a digital state machine from a master controller in an IC-chip testing system.
A single IC-chip (integrated circuit chip) can contain over one-million transistors, and those transistors must be tested before the IC-chip is sold to a customer. Usually, each IC-chip is incorporated into an integrated circuit module (IC-module) before it is tested. In one type of IC-module, the IC-chip is attached to a substrate and covered with a lid. Alternatively, the lid may be left off of the IC-module. In either case, electrical terminals are provided on the substrate which are connected by microscopic conductors in the substrate to the IC-chip.
To test the IC-chips, the complex '524 system (which is referenced under “RELATED CASES”) has been developed. FIG. 1 of the '524 application shows that the '524 system is comprised of several modules 21–24, 31–34, 41–44, 40, 50, 60, 70 and 80. The present invention controls the operation of four digital state machines, a respective one of which is in each of the modules 21–24, from a master controller which is module 70. Thus, for convenience, FIG. 1 from the '524 application is reproduced herein as FIG. 1. Also, TABLE 1 from the '524 application, which describes all of the FIG. 1 modules, is reproduced below.
TABLE 1MODULEDESCRIPTION21Module 21 is a combinationof three subassemblieswhich each perform par-ticular functions. One sub-assembly holds a group ofIC-chips which are to betested. The second sub-assembly supplies elec-trical power to the abovegroup of IC-chips whilethey are tested. The thirdsubassembly sends testsignals to the above groupof IC-chips while they aretested. One structure formodule 21 is shown indetail in FIG. 5, (which isdescribed later).22, 23, 24Each of the modules 22, 23,and 24 perform the samefunctions, and have thesame structure, as module21. The modules 21–24operate independently ofeach other.31Module 31 is a movingmechanism which auto-matically moves module 21horizontally within system10 from a load position toa test position, and visa-versa. In FIG. 1, module21 is shown at the loadposition.32, 33, 34Modules 32, 33, and 34 arerespective moving mechan-isms for the modules 22,23, and 24. Each movingmechanism operates in-dependently to move one ofthe modules 22–24horizontally within thesystem 10 from the loadposition to the testposition, and visa-versa.One structure for themoving mechanisms 31–34 isshown in FIGS. 2 and 4,(which are describedlater).41Module 41 is a temperaturecontrol module for thegroup of IC-chips that areheld by module 21. Thistemperature control module41 moves vertically withinthe system 10 to contactthe group of IC-chips thatare held by module 21 whenthat module is in the testposition. The structure ofthe temperature controlmodule 41 is shown in FIGS.2 and 6 (which aredescribed later).42, 43, 44Modules 42, 43, and 44 arerespective temperaturecontrol modules for themodules 22, 23, and 24.Each temperature controlmodule moves verticallywithin the system 10independently of the othertemperature control mod-ules.40Module 40 is a temperaturecontrol center which isshared by all of thetemperature control modules41–44. One function whichthe temperature controlcenter 40 performs is tocirculate a liquid coolantthrough each of thetemperature control modules41–44. Another functionwhich the temperaturecontrol center 40 performsis to send control signalsto each of the modules41–44 which enable thesemodules to regulate thetemperature of the IC-chipsthat they contact.50Module 50 is a containerplacing mechanism whichplaces several differenttypes of containers, forthe IC-modules, at pre-determined locations belowthe load position of themodules 21–24. Thesecontainers include “source”containers which hold IC-chips that need to beloaded into the modules21–24 so they can be tested,“pass” containers whichhold IC-chips that havebeen tested and passed thetest, and “fail” containerswhich hold IC-chips thathave been tested and failedthe test. The structure ofthe container placingmechanism is shown in FIGS.3A–3B (which is describedlater).60Module 60 is a chip handlermechanism which auto-matically takes IC-modulesfrom the source containersin module 50 and placesthem in each of the modules21–24. Also, module 60automatically takes IC-modules from each of themodules 21–24 and placesthem in a pass container ora fail container withinmodule 60. The structureof the chip handlermechanism is shown inFIG. 2 (which is describedlater).70Module 70 is a mastercontroller for the entiresystem 10. One functionwhich the master controller70 performs is toseparately direct each oneof the modules 21–24 whento start sending testsignals to the IC-chipswhich those modules hold.Another function which themaster controller 70performs is to direct thechip handler mechanism 60when the start loading IC-chips into a particular oneof the modules 21–24, andwhen to start unloading IC-chips from those modules.Those operations are shownin FIGS. 7A and 7B, and aredescribed in conjunctionwith those figures.80Module 80 is a humaninterface to the system 10.This human interfaceincludes a microprocessor81, a computer monitor 82,a computer keyboard 83, anda mouse 84. The micro-processor 81 is coupled viaa communication channel 85to the master controller70.
Additional details of module 21 and the master controller 70 are shown in FIG. 2. There, module 21 is shown as including components 21A–21L. Nodules 22–24 have the same structure as module 21.
Component 21I in each of the modules 21–24 is a digital state machine. All of those digital state machines 21I are coupled to the master controller 70 by an ethernet, as shown. The master controller 70 and the digital state machines 21I interact over the ethernet by a novel method which is the gist of the present invention. However, before proceeding with the details of that method, the remaining components which are in each of the modules 21–24 will be briefly described.
Component 21A is a printed circuit board. This printed circuit board 21A lies in a horizontal plane within module 21. In FIG. 2, a side view of the printed circuit board 21A in the horizontal plane is shown, and the printed circuit board 21A extends perpendicularly into the figure.
Each of the components 21B is a socket that is mounted on the downward facing surface of the printed circuit board 21A. In one particular embodiment, a total of thirty-two sockets 21B are mounted on the printed circuit board 21A. However, the total number sockets 21B on the printed circuit board 21A is a design choice.
Each of the components 21C–21E together constitute one IC-module. Component 21C is a substrate within the IC-module; component 21D is an IC-chip that is attached to one surface of the substrate 21C; and component 21E is a set of terminals that extend from an opposite surface of the substrate 21C. The IC-modules are inserted into the sockets 21B, and are removed therefrom, by the chip-handler mechanism 60 that is shown in FIG. 1.
Each of the components 21F is a springy electrical contact on the upward facing surface of the printed circuit board 21A. These contacts 21F are electrically connected to the IC-chips 21D by the conductors that run through the printed circuit board 21A, the sockets 21B, and the substrates 21C.
Some illustrative examples of the conductors in the printed circuit board 21A are shown in FIG. 2 by dashed lines. The symbol “+V” next to the dashed line indicates that the corresponding conductor carries electrical power at a constant voltage +V to the IC-chip 21D. The symbols “TDI, CK” next to a dashed line indicates that the corresponding conductors carry “TEST DATA IN” signals and “CLOCK” signals to an IC-chip 21D. The symbol “TDO” next to a dashed line indicates that the corresponding conductor carries “TEST DATA OUT” signals from the IC-chip 21D. The symbol “T” next to a dashed line indicates that the corresponding conductor carries a signal from a temperature sensor on one IC-chip 21D which measures the chips' temperature.
Component 21G is another printed circuit board. This printed circuit board 21G is attached to the printed circuit board 21A by bolts 21L and nuts 21K, as shown. The printed circuit board 21G includes electrical conductors which connect to the spring electrical contacts 21F, and some illustrative examples of those conductors are shown in FIG. 2 by dashed lines.
Each of the components 21H is a DC—DC converter that is mounted on the upward facing surface of the printed circuit board 21G. In the FIG. 2 embodiment, one separate DC—DC converter 21H is provided for each IC-chip 21D. These DC—DC converters 21H receive electrical power at an input voltage Vin from a power cable (not shown), and they produce electrical power at the voltage +V which is sent to the IC-chips 21D.
Component 21J is an electrical connector. This connector 21J receives a respective temperature signal T from each of the IC-chips 21D that are held by the sockets 21B. All of the temperature signals T are sent on a cable (not shown) from the socket 21J to the temperature control center 40 in FIG. 1.
In operation, the digital state machine 21I in each of the modules 21–24 performs various functions which are controlled by commands from the master controller 70. For example, one type of command directs the digital state machine to store a particular TDI bit pattern in an internal memory. A second type of command directs the digital state machine 21I to send a stored TDI bit pattern to the IC-chips 21C as a serial stream of bits. A third type of command directs the digital state machine 21I to send each “1” in the TDI bit stream at a particular voltage level. A fourth type of command directs the digital state machine 21I to send the TDI bit stream at a particular frequency.
To completely test the IC-chips 21D, the master controller 70 needs to send dozens of different type of commands to the digital state machine 21I. Further, these commands need to be sent in various sequences which may contain over one-hundred commands.
Now in the prior art, one common method of communicating via an ethernet between two personal computers is known as “TCP/IP over ethernet”. The TCP/IP protocol is defined in terms by an “Internet Reference Model” which is a stack that has four layers. In this stack, the top layer is the “application layer”; the next layer is the “transport layer”; the next layer is the “internet layer”; and the bottom layer is the “network layer”.
The transport layer operates in accordance with a “Transmission Control Protocol” (TCP) which is defined in a standard called RFC703. The internet layer operates in accordance with an “Internet Protocol” (IP) which is defined in a standard called RFC791. The network layer can, as one option, operate in accordance with the ethernet protocol which is defined by a standard called IEEE802.3.
By comparison, the structure and operation of the application layer is not defined by any standards. This is advantageous because it allows TCP/IP over ethernet to be implemented in a wide variety of applications.
However, the present inventor has discovered that when TCP/IP over ethernet is used to send commands in the application layer from the master controller 70 to the digital state machine 21I in the IC-chip testing system of FIGS. 1 and 2, the operation of the TCP/IP/ethernet layers can greatly effect the efficiency with which those commands are sent. In two specific numeral examples, which are described later herein in conjunction with FIGS. 6B and 8B, that efficiency of transmission respectively is just 9.4%, and 7.1%.
Accordingly, a primary object of the present invention is to provide a novel solution to the above efficiency problem.